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preliminary differential-to-lvds buffer/divider w/internal termination ICS889872 idt? / ics? lvds buffer/divider w/internal termination 1 ICS889872ak rev. a august 22, 2007 general description the ICS889872 is a high speed differential-to- lvds buffer/divider w/internal termination and is a member of the hiperclocks? family of high performance clock solutions from idt. the ICS889872 has a selectable 2, 4, 8, 16 output dividers. the clock input has internal termination resistors, allowing it to interface with several differential signal types while minimizing the number of required external components. the device is packaged in a small, 3mm x 3mm vfqfn package, making it ideal for use on space-constrained boards. features ? three lvds outputs ? frequency divide select options: 4, 6: >2ghz, 8, 16: >1.6ghz ? in, nin input can accept the following differential input levels: lvpecl, lvds, cml ? output frequency: >2ghz ? cycle-to-cycle jitter: 1ps (typical) ? total jitter: 10ps (typical) ? output skew: 7ps (typical), qa/nqa outputs ? part-to-part skew: 250ps (typical) ? propagation delay: 750ps (t ypical), qa/nqa outputs ? full 2.5v supply mode ? -40c to 85c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages hiperclocks? ic s ICS889872 16-lead vfqfn 3mm x 3mm x 0.95mm package body k package top view the preliminary information presented herein represents a produc t in pre-production. the noted characteristics are based on ini tial product characterization and/or qualification. integrated device technology, incorporated (idt) reserves the ri ght to change any circuitry or specifications without notice. block diagram pin assignment decoder 2, 4, 8, 16 50 ? 50 ? enable ff enable mux qa nqa qb0 nqb0 qb1 nqb1 nreset/ ndisable in v t v ref_ac s1 s0 nin 5 6 7 8 16 15 14 13 1 2 3 4 12 11 10 9 qb0 nqb0 qb1 nqb1 in v t v ref_ac nin qa nqa v dd nreset/ ndisable s1 v dd gnd s0
ICS889872 differential-to-lvds buffer/divider w/interna l termination preliminary idt? / ics? lvds buffer/divider w/internal termination 2 ICS889872ak rev. a august 22, 2007 table 1. pin descriptions note: pullup refers to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 2 qb0, nqb0 output differential output pair. divide by 2, 4, 8, 16. unused outputs must be terminated with 100w across the pin (qb0/nqb0). lvds interface levels. 3, 4 qb1, nqb1 output differential output pair. divide by 2, 4, 8, 16. unused outputs must be terminated with 100w across the pin (qb1nqb1). lvds interface levels. 5, 6 qa, nqa output differential undivided output pair. lvds interface levels. 7, 14 v dd power power supply pins. 8 nreset/ ndisable input pullup output reset and enable/disable pin. w hen low, resets the divider select, and align bank a and bank b edges. in addition, when low, bank a and bank b will be disabled. input threshold is v dd /2v. includes a 37k ? pullup resistor. lvttl / lvcmos interface levels. 9 nin input inverting differential lvpecl clock input. rt = 50 ? termination to v t . 10 v ref_ac output reference voltage for ac-coupled applications. equal to v dd ? 1.4v (approx.). maximum sink/s ource current is 0.5ma. 11 v t input termination input. leave pin floating. 12 in input non-inverting lvpecl di fferential clock input. rt = 50 ? termination to v t . 13 gnd power power supply ground. 15, 16 s1, s0 input pullup select pins. logic high if left unconnected (16 mode). s0 = lsb. input threshold is vdd/2. 37kw pullup resistor. lvcmos/lvttl interface levels. symbol parameter test conditions minimum typical maximum units r pullup input pullup resistor 37 k ?
ICS889872 differential-to-lvds buffer/divider w/interna l termination preliminary idt? / ics? lvds buffer/divider w/internal termination 3 ICS889872ak rev. a august 22, 2007 function tables table 3a. control input function table note: after nreset switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in figure 1. figure 1. nreset timing diagram table 3b. truth table note 1: on the next negative transition of the input signal. note 2: asynchronous reset/disable function.absolute maximum ratings input outputs nreset qa, qbx nqa, nqbx 0 disabled; low disabled; high 1 enabled enabled inputs outputs nreset/ndisable s 1 s0 bank a bank b 1 0 0 input clock input clock 2 1 0 1 input clock input clock 4 1 1 0 input clock input clock 8 1 1 1 input clock input clock 16 0 x x qa = low, nqa = high; note 1 qbx = low, nqbx = high; note 2 t pd t rr v out swing v dd /2 v in swing nreset in nin nqbx qbx qa nqa
ICS889872 differential-to-lvds buffer/divider w/interna l termination preliminary idt? / ics? lvds buffer/divider w/internal termination 4 ICS889872ak rev. a august 22, 2007 absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = 2.5v 5%, t a = -40c to 85c table 4b. lvcmos/lvttl dc characteristics, v dd = 2.5v 5%, t a = -40c to 85c item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o continuos current surge current 10ma 15ma input current, in, nin 50ma v t current, i vt 100ma input sink/source, i ref_ac 0.5ma operating temperature range, t a -40c to +85c package thermal impedance, ja , (junction-to-ambient) 51.5 c/w (0 lfpm) storage temperature, t stg -65 c to 150 c symbol parameter test conditions minimum typical maximum units v dd positive supply voltage 2.375 2.5 2.625 v i dd power supply current 80 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 2 v dd + 0.3 v v il input low voltage 0 0.8 v i ih input high current v dd = v in = 2.625v 5 a i il input low current v dd = 2.625v, v in = 0v -150 a
ICS889872 differential-to-lvds buffer/divider w/interna l termination preliminary idt? / ics? lvds buffer/divider w/internal termination 5 ICS889872ak rev. a august 22, 2007 table 4c. differential dc characteristics, v dd = 2.5v 5%, t a = -40c to 85c table 4d. lvds dc characteristics, v dd = 2.5v 5%, t a = -40c to 85c ac electrical characteristics table 5. ac characteristics, v dd = 2.5v 5%, t a = -40c to 85c all parameters characterized at 1ghz unless otherwise noted. note 1: measured from the differential input cro ssing point to the differential output crossing point. note 2: specs are design targets. note 3: defined as skew between outputs at the sa me supply voltage and with equal load conditions. measured at the output differential cross points. note 4: this parameter is defined in accordance with jedec standard 65. note 5: defined as skew between outputs on different devices oper ating at the same supply voltages and with equal load conditio ns. using the same type of inputs on each device, the output s are measured at the differential cross points. note 6: the cycle-to-cycle jitter on the input will equal the jitter on the output. the part does not add jitter. symbol parameter test conditio ns minimum typical maximum units r in differential input resi stance (in, nin) 100 ? v ih input high voltage (in, nin) 1.2 v dd v v il input low voltage (in, nin) 0 v dd ? 0.15 v v in input voltage swing 0.15 2.8 v v diff_in differential input voltage swing 0.3 v i in input current (in, nin) 45 ma v ref_ac bias voltage v dd ? 1.35 v symbol parameter test conditio ns minimum typical maximum units v out output voltage swing 350 mv v oh output high voltage 1.475 v v ol output low voltage 0.925 v v ccm output common mode voltage 1.35 v ? v ocm change in common mode voltage 50 mv parameter symbol test conditio ns minimum typical maximum units f max output frequency 2, 4 >2 ghz input frequency 8, 16 >1.6 ghz t pd propagation delay; note 1, 2 in-to-q input swing: <400mv 750 ps input swing: 400mv 750 ps t sk(o) output skew; note 2, 3, 4 qb0-to-qb1 7 ps qa-to-qb 60 ps t sk(pp) part-to-part skew; note 2, 4, 5 250 ps t jit(cc) cycle-to-cycle jitter; note 2, 6 1 ps t jit(j) total jitter; note 2 10 ps t rr reset recovery time; note 2 600 ps t r / t f output rise/fall time; note 2 150 ps
ICS889872 differential-to-lvds buffer/divider w/interna l termination preliminary idt? / ics? lvds buffer/divider w/internal termination 6 ICS889872ak rev. a august 22, 2007 parameter measureme nt information lvds output load ac test circuit part-to-part skew cycle-to-cycle jitter differential input level output skew propagation delay scope qx nqx lvds 2.5v5% power supply +? float gnd v dd nqx qx qy qy t sk(pp) part 1 part 1 ? ? ? ? t cycle n t cycle n+1 t jit(cc) = t cycle n ? t cycle n+1 1000 cycles nqa, nqb[0:1] qa, qb[0:1] , v ih cross points v in v il nin in v dd gnd t sk(o) nqx qx nqy qy t pd nqa, nqb[0:1] qa, qb[0:1] nin in
ICS889872 differential-to-lvds buffer/divider w/interna l termination preliminary idt? / ics? lvds buffer/divider w/internal termination 7 ICS889872ak rev. a august 22, 2007 parameter measurement in formation, continued single-ended & differential input voltage swing output rise/fall time application information wiring the differential input to accept single ended levels figure 2 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v dd /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possib le to the input pin. the ratio of r1 and r2 might need to be adjusted to position the v_ref in the center of the input vo ltage swing. for example, if the input clock swing is only 2.5v and v dd = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. figure 2. single-ended signal driving differential input v in , v out 800mv (typical) v diff_in , v diff_out 1600mv (typical) clock outputs 20% 80% 80% 20% t r t f v od single ended clock input v dd in nin r1 c1 0.1u r2 1k 1k v_ref
ICS889872 differential-to-lvds buffer/divider w/interna l termination preliminary idt? / ics? lvds buffer/divider w/internal termination 8 ICS889872ak rev. a august 22, 2007 differential input with built-in 50 ? termination interface the in /nin with built-in 50 ? terminations accepts lvds, lvpecl, lvhstl, cml, sstl and other differential signals. both signals must meet the v pp and v cmr input requirements. figures 3a to 3e show interface examples for th e hiperclocks in/nin input with built-in 50 ? terminations driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 3a. hiperclocks in/nin input with built-in 50 ? driven by an lvds driver figure 3c. hiperclocks in/nin input with built-in 50 ? driven by a cml driver with built-in 50 ? pullup figure 3e. hiperclocks in/nin input with built-in 50 ? driven by a 3.3v cml driver with built-in pullup figure 3b. hiperclocks in/nin input with built-in 50 ? driven by an lvpecl driver figure 3d. hiperclocks in/nin input with built-in 50 ? driven by an sstl driver in nin vt receiver with built-in 50 ? lvds 3.3v or 2.5v 2.5v zo = 50 ? zo = 50 ? cml - built-in 50 ? pull-up in nin vt receive r with built-in 50 ? 2.5v 2.5v zo = 50 ? zo = 50 ? c1 c2 vt ref_ac 50 ? 50 ? 3.3v cml with built-in pullup 3.3v in nin 2.5v receiver with built-in 50 ? zo = 50 ? zo = 50 ? in nin vt receiver with built-in 50 ? r1 18 lvpecl 2.5v 2.5v zo = 50 ? zo = 50 ? c1 c2 vt ref_ac 50 ? 50 ? 3.3v lvpecl r5 100 - 200 ? r5 1 00 - 200 ? 3.3v in nin 2.5v receiver with built-in 50 ? zo = 50 ? zo = 50 ?
ICS889872 differential-to-lvds buffer/divider w/interna l termination preliminary idt? / ics? lvds buffer/divider w/internal termination 9 ICS889872ak rev. a august 22, 2007 recommendations for unused input pins inputs: lvcmos select pins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. o ut puts: lvds outputs all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating, we recommend that there is no trace attached. epad thermal release path the epad provides heat transfer from the device to the p.c. board. the exposed metal pad on the pcb is connected to the ground plane through thermal vias. to guarantee the device?s electrical and thermal performance, epad must be soldered to the exposed metal pad on the pcb, as shown in figure 4. for further information, please refer to the application note on surface mount assembly of amkor?s thermally /electrically enhance leadframe base package, amkor technology. figure 4. p.c. board for exposed pad thermal release path example exposed metal pad pin solder epad (ground pad) solder pin thermal via pin pad ground plane pin pad
ICS889872 differential-to-lvds buffer/divider w/interna l termination preliminary idt? / ics? lvds buffer/divider w/internal termination 10 ICS889872ak rev. a august 22, 2007 2.5v lvds driver termination figure 5 shows a typical termination for lvds driver in characteristic impedance of 100 ? differential (50 ? single) transmission line environment. for buffer with multiple ldvs driver, it is recommended to terminate the unused outputs. figure 5. typical lvds driver termination 2.5v lvds driver r1 100 ? ? + 2.5v 50 ? 50 ? 100 ? differential transmission line
ICS889872 differential-to-lvds buffer/divider w/interna l termination preliminary idt? / ics? lvds buffer/divider w/internal termination 11 ICS889872ak rev. a august 22, 2007 power considerations this section provides information on power dissipa tion and junction temperature for the ICS889872. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS889872 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 2.5v + 5% = 2.625v, which gives worst case results. power_ max = v dd_max * i dd_max = 2.625v * 80ma = 210mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction te mperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 51.5c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.210w * 51.5c/w = 95.8c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary dependi ng on the number of loaded ou tputs, supply voltage, air flow and the type of board (single layer or multi-layer). table 6. thermal resistance ja for 16 lead vfqfn, forced convection ja by velocity linear feet per minute 0 multi-layer pcb, jedec standard test boards 51.5c/w
ICS889872 differential-to-lvds buffer/divider w/interna l termination preliminary idt? / ics? lvds buffer/divider w/internal termination 12 ICS889872ak rev. a august 22, 2007 reliability information table 7. ja vs. air flow table for a 16 lead vfqfn transistor count the transistor count for ICS889872 is: 323 pin compatible with sy89872u package outline and package dimensions package outline - k suffix for 16 lead vfqfn table 8. package dimensions reference document: jede c publication 95, mo-220 ja by velocity linear feet per minute 0 multi-layer pcb, jedec standard test boards 51.5c/w jedec variation: veed-2/-4 all dimensions in millimeters symbol minimum maximum n 16 a 0.80 1.00 a1 00.05 a3 0.25 ref. b 0.18 0.30 n d & n e 4 d & e 3.00 basic d2 & e2 1.00 1.80 e 0.50 basic l 0.30 0.50 to p view index area d cham fer 4x 0.6 x 0.6 max optional anvil singula tion a 0. 0 8 c c a3 a1 s eating plan e e2 e2 2 l (n -1)x e (r ef.) (ref. ) n & n even n e d2 2 d2 (ref.) n & n odd 1 2 e 2 (ty p.) if n & n are even (n -1)x e (re f.) b th er mal ba se n or
ICS889872 differential-to-lvds buffer/divider w/interna l termination preliminary idt? / ics? lvds buffer/divider w/internal termination 13 ICS889872ak rev. a august 22, 2007 ordering information table 9. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature ICS889872ak 872a 16 lead vfqfn tube -40 c to 85 c ICS889872akt 872a 16 lead vfqfn 2500 tape & reel -40 c to 85 c ICS889872aklf tbd ?lead-free? 16 lead vfqfn tube -40 c to 85 c ICS889872aklft tbd ?lead-free? 16 lead vfqfn 2500 tape & reel -40 c to 85 c while the information presented herein has been checked for both a ccuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications, such as those requiring high reliability or other ext raordinary environmental requirements are not recommended without additional processing by idt. idt reserves t he right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support device s or critical medical instruments.
www.idt.com ? 2007 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited 321 kingston road leatherhead, surrey kt22 7tu england +44 (0) 1372 363 339 fax: +44 (0) 1372 378851 for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 innovate with idt and accelerate your future netw orks. contact: www.idt.com ICS889872 differential-to-lvds buffer/divide r w/internal termination preliminary

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